The present invention relates to a system for supplying an address to a memory unit.
The art of memory multiplexing, that is, supplying a row address and a column address by time division on an address bus to a memory matrix of a dynamic RAM is described in, for example, a Manual of Hitachi IC Memory, March 1990, pp. 91-92.
The U.S. Pat. No. 4,694,454 issued to Y. Matsuura on Sep. 15, 1987 discloses the refresh operation in a dynamic memory, which description is herein introduced by reference to the number thereof.
In a conventional dynamic memory device, as described in "Nikkei Micro-Devices," March 1989, p.p. 42-43, the refresh rate of 2048 cycles has been employed for the period of 32 ms for 16 megabits. In other words, the refreshing has been effected by division of (1/2) .sqroot.memory capacity in a predetermined length of time. This refresh rate is equivalent to 512 for a 1-megabit memory device, and 1024 for a 4-megabit memory device.
The 16-megabit memory device of what is called the next generation type has therefore a refresh cycle of 2048. With the increase in the number of bits activated or refreshed, however, the power consumption is undesirably increased for each cycle. In view of this, the recent tendency is toward reducing the number of bits activated for each cycle by increasing the refresh cycles to 4096 equivalent to .sqroot.memory capacity.
In such a case, 12 bits (PA.sub.0.about.11) of row address in the multiplex address line (A.sub.0.about.11) supplied to the memory device represents a refresh address. As a result, a 16-megabit memory device having a configuration of 4 mega words.times.4 bits is addressed by 12 bits or row address (RA.sub.0.about.11) and 10 bits of column address (CA.sub.0.about.9). An address is thus supplied by ten bits of multiplex address line (A.sub.0.about.9) and 2 bits of nonmultiplex address line (A.sub.10.about.11).
A conventional 4-megabit memory device having a configuration of 4 megawords.times.one bit, on the other hand, is of a type of supplying an address by 11 bits of multiplex address line (A.sub.0.about.10) since 2K.times.2K=4M as well known.
In other words, there are two types of memory device having the same address width, one supplied with an address partly nonmultiplexed but the remainder multiplexed, and the other supplied with all addresses multiplexed. Since alternation of generation of a memory chip used in a memory card is faster that the lifetime of the system, the parallel use of different types of cards is indispensable in order to steadily realize a higher performance of the system in operation.
In a conventional storage unit using the two types of memory devices in parallel, the problem is that the two types of memory devices are required to be discriminated and the storage addresses supplied to the memory address line are required to be controlled separately by switching in spite of the fact that they have the same address width.